Defect-Oriented Test: Effectiveness in High Volume Manufacturing

This article describes a defect-oriented test (DOT) approach, which enables complete physical defect-based automatic pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical (TCA)-based methods are presented needed DOT views to enable DOT-based patterns detecting all cell-internal and as well cell-external defects. The major aim these new is further reduce defect rate manufactured ICs, in addition what already achieved with traditional cell-aware (CAT) fault models. We present results, including reduction defective parts per million (DPPM), from large 14-nm FinFET design, correlation system-level-test (SLT) fails. For second, mature 160-nm automotive mixed-signal sensor we high-volume production again measured DPPM, provide coverage figures moving away counting detected faults calculating TCA reported chip level coverage.